1. Field of the Invention
The present invention relates to a differential amplifier, and more specifically to a differential amplifier constituted of bipolar transistors.
2. Description of Related Art
Referring to FIG. 8, there is shown a circuit diagram illustrating one example of a prior art differential amplifier constituted of bipolar transistors. In brief, the shown differential amplifier includes a pair of NPN bipolar transistors Q1 and Q2 having bases connected to a pair of input terminals IN1 and IN2, respectively, between which a differential input voltage VIN is applied Collectors of the transistors Q1 and Q2 are connected to a power supply voltage VCC through load resistors R1 and R2, respectively. In addition, the collectors of the transistors Q1 and Q2 are connected to a pair of output terminals OUT1 and OUT2, respectively, from which a differential output voltage VOUT is obtained. Emitters of the transistors Q1 and Q2 are connected to ground through current sources I1 and I2 having a constant current I0, respectively. The emitters of the transistors Q1 and Q2 are connected to each other through an emitter feedback resistor R3.
The differential amplifier as shown in FIG. 8, constituted of bipolar transistors and including the emitter feedback resistor, is used as a differential amplifier having a relatively wide input voltage range which can be approximately deemed to operate linearly. In addition, the shown differential amplifier also has another advantage that a gain precision can be easily obtained since a nominal gain is given by a ratio between the emitter feedback resistor and the load resistors.
However, when the differential amplifier as shown in FIG. 8 is used as an input buffer in an analog-to-digital converter, since a high linearity is required, it is an ordinary practice to make improvement in order to elevate the linearity.
Now, assuming R1=R2=1000.OMEGA., R3=2000.OMEGA. and I0=0.25 mA in the differential amplifier as shown in FIG. 8, the result of a "SPICE" (Simulation Program with Integrated Circuit Emphasis) simulation will be described in the following:
FIG. 9 is a graph illustrating a relation between a differential input voltage VIN and a non-linear error VD in the differential amplifier as shown in FIG. 8. Here, VD is a difference between a differential output voltage VOUT=VOUT (VIN) and a tangential line VL=VL (VIN) in differential output voltage VOUT (VIN) at the time of VIN=0V. EQU VD=VOUT(VIN)-VL(VIN)
Accordingly, VD is indicative of the non-linearity in the differential output voltage VOUT. In the following, for purposes of convenience, this VD will be called a non-linear error.
If the differential output voltage VOUT has a complete linearity in relation to the differential input voltage VIN, the non-linear error VD ceaselessly becomes zero.
For purposes of convenience, assume that if the non-linear error VD is within the range of .+-.1 mV, it can be deemed to be linear. In this case shown in FIG. 9, the range of the differential input voltage VIN permitting the linear operation becomes .+-.220 mV. On the other hand, since the differential output voltage VOUT of the shown differential amplifier is cramped at .+-.500 mV, and since the nominal gain is 1 (=2.times.R1/R3), a maximum operable range of the differential input voltage VIN is also .+-.500 mV. However, the shown differential amplifier can operate in a linear operating mode in only a range which is a half of the maximum operable range
In addition, the gain at the differential input voltage VIN=0V, namely, the inclination of the tangential line VL, is 0.86, which is smaller than the nominal gain 1 at some degree.
The non-linear operation of the differential amplifier shown in FIG. 8 is mainly attributable to the circumstances that a base-emitter voltage (VBE) of the bipolar transistors Q1 and Q2 non-linearly changes in relation to a collector current (IC).
Now, one prior art example for improving the linearity will be described with reference to FIG. 10, which is a circuit diagram illustrating another prior art example of the differential amplifier, which is constituted to improve the linearity of the differential amplifier shown in FIG. 8 and which is shown in FIG. 7(a) of T. Kumamoto et at, "A 10-bit 50 MS/s 50 mW A/D Converter with Differential-Voltage Subconverter", Technical Report of IEICE (The Institute of Electronics, Information and Communication Engineers (in Japan)), ED93-47, ICD9346 (1994-06), pp17-22. In FIG. 10, elements corresponding to those shown in FIG. 8 are given the same Reference Numerals, and explanation will be omitted.
In the differential amplifier shown in FIG. 10, diodes D1 and D2 are inserted between the power supply voltage VCC and the load resistors R1 and R2, respectively. In this example, the non-linearity is compensated by the diodes D1 and D2, so that a linear differential output voltage is obtained.
Actually, assuming R1=R2=R3/2, the differential output voltage VOUT is expressed as follows: ##EQU1## where VBE1, VBE2, VD1 and VD2 are a base-emitter voltage of the bipolar transistors Q1 and Q2, and a forward-direction voltage drop of the diodes D1 and D2, respectively. In addition, VBE1 is substantially equal to VD1 (since a current flowing through Q1 is substantially equal to a current flowing through D1), and also VBE2 is substantially equal to VD2. Thus, the result expressed by the above equation is obtained
Now, assuming R1=R2=1000.OMEGA., R3=2000.OMEGA. and I0=0.25 mA in the differential amplifier as shown in FIG. 10, the result of the SPICE simulation will be described in the following:
FIG. 11 is a graph illustrating a relation between a differential input voltage VIN and a non-linear error VD in the differential amplifier as shown in FIG. 10. As seen from comparison between FIG. 9 and FIG. 11, the differential amplifier shown in FIG. 10 has a linearly operating range wider than that of the differential amplifier shown in FIG. 8. Namely, the differential amplifier shown in FIG. 10 has an improved linearity.
In addition, the gain at the differential input voltage VIN=0V, namely, the inclination of the tangential line VL, is 0.9808, which is slightly less than the nominal gain 1 but is nearer to 1, in comparison with the differential amplifier shown in FIG. 8.
However, since the differential amplifier shown in FIG. 10 includes the diode connected in series with the load resistor, a common-mode output potential drops by the forward-direction voltage drop (about 0.8V) of the diode, and therefore, when the power supply voltage is low, a next-stage circuit directly receiving the output of the differential amplifier becomes difficult to properly operate at a low power supply voltage.
Referring to FIG. 12, there is shown a circuit diagram illustrating still another prior art example of the differential amplifier, which is shown in Japanese Patent Application Pre-examination Publication No. JP-A-57-160207, which corresponds to U.S. Pat. No. 4,496,860, the content of which is incorporated by reference in its entirety into this application. In FIG. 12, elements corresponding to those shown in FIG. 8 are given the same Reference Numerals, and explanation will be omitted
The differential amplifier shown in FIG. 12 includes a non-linear distortion compensating circuit 101 provided as an input stage receiving a differential input voltage, and a differential buffer 102 constructed completely similarly to the differential amplifier shown in FIG. 8. The non-linear distortion compensating circuit 101 includes a pair of NPN bipolar transistors Q3 and Q4 having collectors connected directly to a power supply voltage VCC. Bases of the transistors Q3 and Q4 are connected to a pair of input terminals IN1 and IN2, respectively, between which a differential input voltage VIN is applied. Emitters of the transistors Q3 and Q4 are connected to the bases of the transistors Q1 and Q2, respectively.
The non-linear distortion compensating circuit 101 also includes another pair of NPN bipolar transistors Q5 and Q6 each having a base cross-connected to a collector of the other of the pair of NPN bipolar transistors Q5 and Q6. The collectors of the NPN bipolar transistors Q5 and Q6 are connected to the emitters of the transistors Q3 and Q4, respectively. Emitters of the transistors Q5 and Q6 are connected to ground through current sources I3 and I4, respectively. The emitters of the transistors Q5 and Q6 are connected to each other through an emitter feedback resistor R4.
In the differential amplifier shown in FIG. 12, a current of an emitter follower (the bipolar transistors Q3 and Q4) in the non-linear distortion compensating circuit 101 changes dependently upon the input differential voltage VIN (input signal), and a base-emitter voltage VBE of the bipolar transistors Q3 and Q4 changes dependently upon the change of the current of the emitter follower, with the result that the change of the base-emitter voltage VBE of the bipolar transistors Q1 and Q2 in the differential buffer 102 is canceled, so that a linear differential output voltage can be obtained.
Actually, assuming R1=R2=R3/2=R4/2, the differential output voltage VOUT of the differential amplifier shown in FIG. 12 is expressed as follows: ##EQU2## where VBE1, VBE2, VBE3 and VBE4 are a base-emitter voltage of the bipolar transistors Q1, Q2, Q3 and Q4, respectively. In addition, VBE1 is substantially equal to VBE4 (since a current flowing through Q1 is substantially equal to a current flowing through Q4), and also VBE2 is substantially equal to VBE3. Thus, the result expressed by the above equation is obtained
Differently from the differential amplifier shown in FIG. 10, since the differential amplifier shown in FIG. 12 has no drop in the common-mode output voltage, a next-stage circuit directly receiving the output of the differential amplifier becomes can properly operate at a low power supply voltage. In addition, the nominal gain is not necessarily required to be 1.
For reference, the gain at the differential input voltage VIN=0V, namely, the inclination of the tangential line VL, is 0.9718, which is slightly less than the nominal gain 1.
Actually, however, because of a base current of the bipolar transistors Q1, Q2, Q3 and Q4 which was ignored in the above mentioned equation, improvement of the linearity is not so good, and therefore, it has a disadvantage that the linearly operating range is narrow.
Now, assuming R1=R2=1000.OMEGA., R3=2000.OMEGA. and I0=0.25 mA in the differential amplifier as shown in FIG. 12, the result of the SPICE simulation will be described in the following:
FIG. 13 is a graph illustrating a relation between a differential input voltage VIN and a non-linear error VD in the differential amplifier as shown in FIG. 12. As shown in FIG. 13, the linearly operating range is about .+-.300 mV, which cannot be said to be sufficiently wide.
Next, influence of the base current will be described.
VBE1 and VBE4 in this prior art differential amplifier shown in FIG. 12 are given by the following equations: ##EQU3## where V.sub.T is a thermal voltage (V.sub.T =kT/q; k=Boltzmann constant, T=absolute temperature, q=elementary charge), IS is a saturation current, IC1 to IC6 and IB1 to IB6 are a collector current and a base current of the transistors Q1 to Q6, and .beta. is a current gain. In addition, since the differential amplifier shown in FIG. 12 has a current mirror structure, a relation of IC6=IC1 and IB2=IB5 holds. By using this relation, the equation was modified.
The currents IC1 to IC6 change upon the change of the differential input voltage VIN, but if the change of VBE1 is equal to the change of VB4, the linear operation of the circuit is obtained Actually, however, since the base currents exist, it would be understood from the above equation that the change of VBE1 never becomes equal to the change of VBE4.